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asahi kasei [AK4569] ms0292-e-01 2005/07 - 1 - general description the AK4569 is a 20bit codec with built-in input pga and headphone amplifier. the AK4569 includes a microphone/line input selector and an alc circuit for input, and a mono line output buffer, analog volume controls and stereo headphone amplifier for output. the AK4569 also features an analog mixing circuit that allows easy interfacing in mobile phone and portable communication designs. the integrated headphone amplifier features ?pop-fre e? power-on/off, a mute control and delivers 8.7mw of power into 16 ? load via 6.8 ? series resistor. the AK4569 is housed in a 28pin qfn package, making it suitable for portable applications. feature ? 2ch 20bit adc - s/n: 89db - single-ended input - 2 stereo inputs selector - analog input pga: +32db ? 19db, mute, 0.5db step (mic input) +20db ? 31db, mute, 0.5db step (line input) - digital hpf for dc-offset cancellation - i/f format: 20bit msb justified, i 2 s ? 2ch 20bit dac - i/f format: i 2 s, 20bit msb justified, 20bit/16bit lsb justified - digital att: 0db ? 127db, mute, 0.5db step (soft transition) - soft mute - digital de-emphasis filter: 32khz, 44.1khz and 48khz - bass boost function ? sampling rate: 8khz 48khz ? system clock: 256fs/384fs/512fs - input level: cmos or 1vpp analog input ? analog mixing circuit ? mono lineout - analog volume: 0db ? 30db, mute, 2db step ? headphone amplifier - output power: 8.7mw x 2ch @16 ? load & 6.8 ? series resistor - s/n: 90db ? p interface: 3-wire ? power management ? power supply: 2.7v 3.6v ? power dissipation: 15ma ? ta: ? 40 85 c ? small package: 28pin qfn (5.2mm x 5.2mm, 0.5mm pitch) 20-bit stereo codec with ipga & hp-amp AK4569
asahi kasei [AK4569] ms0292-e-01 2005/07 - 2 - vcom sdto lrck bick adc hpf audio i/f controller ipga a inl1 a inl2 a inr1 a inr2 vcom hp-amp hpl dac hpr mout lin rin min hvdd hvss mutet avdd avss boost datt sdti control mclk csn cclk cdti register pdn dvdd dvss hp-amp ipga & adc mout dac vref vref figure 1. block diagram
asahi kasei [AK4569] ms0292-e-01 2005/07 - 3 - ? ordering guide AK4569vn ? 40 +85 c 28pin qfn (0.5mm pitch) akd4569 evaluation board for AK4569 ? pin layout pdn ainl1 1 csn 28 2 cclk 3 cdti 4 lrck 5 mclk 6 bick 7 ainr1 27 ainl2 26 25 24 avss 23 vcom 22 sdti 8 sdto 9 dvdd 10 dvss 11 hvss 12 13 hpr 14 21 20 19 18 17 16 15 vref lin rin min mout mutet hpl to p vi e w hvdd ainr2 avdd ? comparison table between ak4566 and AK4569 function ak4566 AK4569 dac digital filter stopband attenuation (min) 43db 59db passband ripple (max) 0.06db 0.01db frequency response including analog filter (0 20.0khz) 0.5db 1.0db the condition to stop the external clocks. pdn pin = ?l? pdn pin = ?l? or pmadc=pmdac bits = ?0?
asahi kasei [AK4569] ms0292-e-01 2005/07 - 4 - pin/function no. pin name i/o function 1 pdn i power-down pin when ?l?, the AK4569 is in power-down mode and is held in reset. the AK4569 should always be reset upon power-up. 2 csn i control data chip select pin 3 cclk i control clock input pin 4 cdti i control data input pin 5 lrck i l/r clock pin this clock determines which audio channel is currently being output on sdto pin and input on sdti pin. 6 mclk i master clock input pin 7 bick i serial bit clock pin this clock is used to latch audio data. 8 sdti i audio data input pin 9 sdto o audio data output pin sdto pin goes to dvss when pdn pin is ?l?. 10 dvdd - digital power supply pin 11 dvss - digital ground pin 12 hvss - ground pin for headphone amplifier 13 hvdd - power supply pin for headphone amplifier 14 hpr o rch headphone amplifier output pin hpr pin goes to hvss when pdn pin is ?l?. 15 hpl o lch headphone amplifier output pin hpl pin goes to hvss when pdn pin is ?l?. 16 mutet o mute time constant control pin a capacitor for mute time constant should be connected between mutet pin and hvss pin. mutet pin goes to hvss when pdn pin is ?l?. 17 mout o mono analog output pin mout pin goes to hi-z when pdn pin is ?l?. 18 min i mono analog input pin 19 rin i rch analog input pin 20 lin i lch analog input pin 21 vref o reference voltage output pin, 2.1v (typ, respect to avss) normally connected to avss pin with 0.1 f ceramic capacitor in parallel with a 4.7 f electrolytic capacitor. vref pin goes to avss when pdn pin is ?l?. 22 vcom o common voltage output pin, 1.25v (typ, respect to avss) normally connected to avss pin with 0.1 f ceramic capacitor in parallel with a 2.2 f electrolytic capacitor. vcom pin goes to avss when pdn pin is ?l?. 23 avss - analog ground pin 24 avdd - analog power supply pin 25 ainr2 i rch analog input 2 pin for adc (mic input) 26 ainl2 i lch analog input 2 pin for adc (mic input) 27 ainr1 i rch analog input 1 pin for adc (line input) 28 ainl1 i lch analog input 1 pin for adc (line input) note: no digital input pins must be left floating.
asahi kasei [AK4569] ms0292-e-01 2005/07 - 5 - ? handling of unused pin the unused i/o pins should be processed appropriately as below. classification pin name setting analog hpr, hpl, mout, ainr2, ainl2, ainr1, ainl1 these pins should be open. sdto this pin should be open. digital sdti this pin should be connected to dvss. absoluate maximum rating (avss, dvss, hvss=0v; note 1) parameter symbol min max units power supplies analog digital hp-amp |avss ? hvss| (note 2) |avss ? dvss| (note 2) avdd dvdd hvdd ? gnd1 ? gnd2 ? 0.3 ? 0.3 ? 0.3 - - 4.6 4.6 4.6 0.3 0.3 v v v v v input current (any pins except for supplies) iin - 10 ma analog input voltage (note 3) vina ? 0.3 (avdd+0.3) or 4.6 v digital input voltage (note 4) vind ? 0.3 (dvdd+0.3) or 4.6 v ambient temperature ta ? 40 85 c storage temperature tstg ? 65 150 c note 1. all voltages with respect to ground. note 2. avss, dvss and hvss must be connected to the same analog ground plane. note 3. min, rin, lin, ainr2, ainl2, ainr1, ainl1 pins. max is smaller value between (avdd+0.3) and 4.6v. note 4. pdn, csn, cclk, cdti, lrck, mclk, bick, sdti pins. max is smaller value between (dvdd+0.3) and 4.6v. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommend operating conditions (avss, dvss, hvss=0v; note 1) parameter symbol min typ max units power supplies analog digital (note 5) hp-amp avdd dvdd hvdd 2.5 2.5 or (avdd ? 0.3) 2.5 3.0 3.0 3.0 3.6 3.6 or (avdd+0.3) 3.6 v v v note 1. all voltages with respect to ground. note 5. min is larger value between 2.5v and (avdd ? 0.3). max is smaller value between 3.6v and (avdd+0.3). * akm assumes no responsibility for usage be yond the conditions in this datasheet.
asahi kasei [AK4569] ms0292-e-01 2005/07 - 6 - analog characteristics (ta=25 c; avdd=dvdd=hvdd=3.0v, avss =dvss=hvss=0v; fs=44.1khz; boost off; signal frequency =1khz; measurement band width=20hz 20khz; unless otherwise specified) parameter min typ max units adc resolution 20 bit ipga characteristics: (ainl1, ainr1 pins) (line in) input voltage 1.35 1.5 1.65 vpp input resistance 25 50 75 k ? step size 0.1 0.5 0.9 db gain control range ? 31 +20 db ipga characteristics: (ainl2, ainr2 pins) (mic in) input voltage 1.35 1.5 1.65 vpp input resistance 6 12.5 19 k ? step size 0.1 0.5 0.9 db gain control range ? 19 +32 db adc characteristics: (note 6) s/(n+d) ( ? 1db input) 74 84 db d-range ( ? 60db input, a-weighted)) 82 89 db s/n (a-weighted) 82 89 db interchannel isolation 80 100 db interchannel gain mismatch 0.2 0.5 db power supply rejection (note 11) - 50 - db dac resolution 20 bit headphone-amp: (hpl/hpr pins) (note 7) load impedance is a serial connection with r l =22.8 ? and c l =100 f. s/(n+d) (0dbfs output) 50 70 db d-range ( ? 60dbfs output, a-weighted) 82 90 db s/n (a-weighted) 82 90 db interchannel isolation 70 90 db interchannel gain mismatch 0.2 0.5 db load resistance (note 8) 20 ? load capacitance (c1 in figure 2) (c2 in figure 2) (note 9) 30 300 pf pf output voltage 1.35 1.5 1.65 vpp power supply rejection (note 11) - 50 - db mono output: (mout pin) (note 10) s/(n+d) (0dbfs output) 70 84 db s/n (a-weighted) 82 90 db load resistance (note 8) 10 k ? load capacitance 30 pf output voltage 1.35 1.5 1.65 vpp power supply rejection (note 11) - 50 - db output volume: (mout pin) step size 1 2 3 db gain control range ? 30 0 db note 6. the signal inputs are ainl1/ainr1 or ainl2/ainr2. the value of the ipga is set to 0db. on-chip hpf cancels the ipga and adc offsets. note 7. dacl=dacr= ?1?, minl=minr= lin=rin= ?0?, a nd attl=attr=0db. note 8. ac load note 9. a resistor greater than 6.8 ? is inserted in series. note 10. dacm= ?1?, linm=rinm=minm= ?0?, attl=attr=attm=0db, and common mode signal is input to l/rch of dac. note 11. psr is applied to avdd, dvdd and hvdd with 1khz, 50mvpp.
asahi kasei [AK4569] ms0292-e-01 2005/07 - 7 - parameter min typ max units analog input: (lin/rin/min pins) input resistance 25 50 75 k ? gain lin/rin mout min mout, lin/min hpl, rin/min hpr ? 7 ? 1 ? 6 0 ? 5 +1 db db power supplies power supply current normal operation (pdn= ?h?) avdd + dvdd + hvdd (note 12) power-down mode (pdn= ?l?) avdd + dvdd + hvdd (note 13) 15 1 24 100 ma a note 12. all blocks are powered-up (pmvcm=pmadc=pmdac=pmhpl=pmhpr=pmmo= ?1?), and hp-amp output is off. avdd=9ma(typ), dvdd=3ma(typ), hvdd=3ma(typ). 9ma(typ) at playback only (pmvcm=pmdac=pmhpl=pmhpr=pmmo= ?1?, pmadc= ?0?). avdd=4ma(typ), dvdd=2ma(typ), hvdd=3ma(typ). note 13. all digital input pins including clock pins (mclk, bick and lrck) are held at dvdd or dvss. pdn pin is held at dvss. + - + hp-amp > 6.8 16 ? 100uf hpl, hpr c1 c2 figure 2. headphone amp output circuit
asahi kasei [AK4569] ms0292-e-01 2005/07 - 8 - filter characteristics (ta=25 c; avdd, dvdd, hvdd=2.5 3.6v; fs=44.1khz; dem=off; boost=off) parameter symbol min typ max units adc digital filter (lpf): passband (note 15) 0.1db ? 1.0db ? 3.0db pb 0 - - 20.0 21.1 17.4 - - khz khz khz stopband (note 15) sb 25.7 khz passband ripple pr 0.1 db stopband attenuation sa 65 db group delay (note 16) gd - 17.0 - 1/fs group delay distortion ? gd 0 s adc digital filter (hpf): frequency response (note 15) ? 3db ? 0.5db ? 0.1db fr 3.4 10 22 hz hz hz dac digital filter: (note 14) passband (note 15) 0.1db ? 0.7db ? 6.0db pb 0 - - 20.0 22.05 19.6 - - khz khz khz stopband (note 15) sb 25.2 khz passband ripple pr 0.01 db stopband attenuation sa 59 db group delay (note 16) gd - 16.8 - 1/fs group delay distortion ? gd 0 s dac digital filter + analog filter: (note 14)(note 17) frequency response 0 20.0khz fr - 1.0 - db boost filter: (note 17) (note 18) min 20hz 100hz 1khz fr - - - 5.74 2.92 0 - - - db db db mid 20hz 100hz 1khz fr - - - 5.94 4.71 0.14 - - - db db db frequency response max 20hz 100hz 1khz fr - - - 16.04 10.55 0.3 - - - db db db note 14. boost off (bst1-0 = ?00?) note 15. the passband and stopband frequencies scale with fs. for example (dac), pb=0.44*fs(@ 0.1db), sb=0.57*fs(@ ? 59db). note 16. this is the calculated delay time caused by digital filtering. this time is measured from the input of analog signal to setting the 20 bit data of both channels on input register to the output register of adc. this time also includes group delay of hpf. for dac, this time is from setting the 20 bit data of both channels on input register to the output of analog signal. note 17. dacl ? hpl, dacr ? hpr, dacl/r ? mout. note 18. these frequency responses scale with fs. if hi gh-level signal is input, the AK4569 clips at low frequency.
asahi kasei [AK4569] ms0292-e-01 2005/07 - 9 - figure 3. boost frequency (fs=44.1khz) dc characteristics (ta=25 c; avdd, dvdd, hvdd = 2.5 3.6v) parameter symbol min typ max units high-level input voltage low-level input voltage input voltage at ac coupling (note 19) vih vil vac 70 % dvdd - 1.0 - 30 % dvdd v v vpp high-level output voltage (iout = ? 100 a) low-level output voltage (iout = 100 a) voh vol dvdd ? 0.4 - - - - 0.4 v v input leakage current iin - - 10 a note 19. when ac coupled capacitor is connected to mclk pin. boost frequency (fs=44.1khz) -25 -20 -15 -10 -5 0 0.01 0.1 1 10 frequency [khz] output level [db] min mid max
asahi kasei [AK4569] ms0292-e-01 2005/07 - 10 - switching characteristics (ta=25 c; avdd, dvdd, hvdd = 2.5 3.6v: c l = 20pf) parameter symbol min typ max units master clock timing frequency pulse width low (note 20) pulse width high (note 20) ac pulse width (note 21) fclk tclkl tclkh tacw 2.048 0.4/fclk 0.4/fclk 0.4/fclk 24.576 mhz ns ns ns lrck timing frequency duty cycle fs duty 8 45 44.1 48 55 khz % serial interface timing (note 22) bick period bick pulse width low pulse width high lrck edge to bick ? ? (note 23) bick ? ? to lrck edge (note 23) lrck to sdto(msb) bick ? ? to sdto sdti hold time sdti setup time tbck tbckl tbckh tlrb tblr tlrs tbsd tsdh tsds 325.5 130 130 50 50 50 50 80 80 ns ns ns ns ns ns ns ns ns control interface timing cclk period cclk pulse width low pulse width high cdti setup time cdti hold time csn ?h? time csn ? ? to cclk ? ? cclk ? ? to csn ? ? tcck tcckl tcckh tcds tcdh tcsw tcss tcsh 200 80 80 40 40 150 50 50 ns ns ns ns ns ns ns ns power-down & reset timing pdn pulse width (note 24) pmadc ? ? to sdto valid (note 25) tpd tpdv 150 2081 ns 1/fs note 20. except ac coupling. note 21. pulse width to ground level when mclk is connected to a capacitor in series and a resistor is connected to ground. (refer to figure 4.) note 22. refer to ?serial data interface?. note 23. bick rising edge must not occur at the same time as lrck edge. note 24. the AK4569 can be reset by bringing pdn= ?l? to ?h? only upon power up. note 25. this is the count of lrck ? ? from pmadc bit=?1?.
asahi kasei [AK4569] ms0292-e-01 2005/07 - 11 - ? timing diagram mclk input measurement point a vss tacw t acw a vss 1/fclk 1000pf 100k ? figure 4. mclk ac coupling timing 1/fclk tclkl vih tclkh mclk vil 1/fs vih lrck vil tbck tbckl vih tbckh bick vil figure 5. clock timing
asahi kasei [AK4569] ms0292-e-01 2005/07 - 12 - tlrb lrck vih bick vil tlrs sdto 50%dvdd tbsd vih vil tblr tsds sdti vih vil tsdh figure 6. serial interface timing tcss csn vih cclk vil vih cdti vil vih vil c1 c0 r/w a4 tcckl tcckh tcds tcdh figure 7. write command input timing csn vih cclk vil vih cdti vil vih vil d3 d2 d1 d0 tcsw tcsh figure 8. write data input timing
asahi kasei [AK4569] ms0292-e-01 2005/07 - 13 - csn vih vil tpdv sdto tpd 50%dvdd pdn vil figure 9. power-down & reset timing
asahi kasei [AK4569] ms0292-e-01 2005/07 - 14 - operation overview ? system clock the external clocks required to operate the AK4569 are mclk(256fs/384fs/512fs), lrck(f s) and bick. the master clock (mclk) should be synchronized with sampling clock (lrck). the phase between these clocks does not matter. the frequency of mclk is detected automatically, and the internal master clock becomes the appropriate frequency. table 1 shows system clock example. lrck mclk (mhz) bick (mhz) fs 256fs 384fs 512fs 64fs 8khz 2.048 3.072 4.096 0.512 11.025khz 2.8224 4.2336 5.6448 0.7056 12khz 3.072 4.608 6.144 0.768 16khz 4.096 6.144 8.192 1.024 22.05khz 5.6448 8.4672 11.2896 1.4112 24khz 6.144 9.216 12.288 1.536 32khz 8.192 12.288 16.384 2.048 44.1khz 11.2896 16.9344 22.5792 2.8224 48khz 12.288 18.432 24.576 3.072 table 1. system clock example external clocks (mclk, bick and lrck) are needed to ope rate adc or dac. all external clocks (mclk, bick and lrck) should always be present whenever the adc or dac is in normal operation mode (pmadc bit = ?1? or pmdac bit = ?1?). if these clocks are not provided, the AK4569 may dr aw excess current and will not operate properly because it utilizes these clocks for internal dynamic refresh of registers. if the external clocks are not present, AK4569 should be placed in power-down mode (pdn pin = ?l? or pmadc bit = pmdac bit = ?0?). when mclk is input with ac coupling, the mckac bit should be set to ?1?. if mclk with ac coupling stops, mckpd bit should be set to ?1?. for low sampling rates, outband noise causes both dr and s/n to degrade. dr and s/n are improved by setting dfs bit to ?1?. table 2 shows s/n of dac output for both the hp-amp and mout. when the dfs bit is ?1?, mclk needs 512fs. during normal operation, when the adc or dac sampling frequency is changed (pmadc bit = ?1? or pmdac bit = ?1?), the dac output should be soft-muted or ?0? data should be input to avoid pop noise. s/n (fs=8khz, a-weighted) dfs fs mclk hp-amp mout 0 8khz 48khz 256fs/384fs/512fs 84db 84db default 1 8khz 24khz 512fs 90db 88db table 2. relationship among fs, mclk frequency and s/n of hp-amp and mout
asahi kasei [AK4569] ms0292-e-01 2005/07 - 15 - ? serial data interface the AK4569 interfaces with external systems via the bick, lrck, sdto and sdti pins. four data formats are available and are selected by setting dif1 and dif0 bits (t able 3). mode 0 of sdti is compatible with existing 16bit dacs and digital filters. mode 1 of sdti is a 20bit version of mode 0. mode 2 of sdti is similar to akm adcs and many dsp serial ports. mode 3 is compatible with the i 2 s serial data protocol. in sdti modes 2 and 3, the following formats are also valid: 16-bit data followed by four zeros and 18-bit data followed by two zeros. in all modes, the serial data is msb first and 2?s complement format. mode dif1 dif0 sdto sdti bick lrck 0 0 0 20bit, msb justified 16bit, lsb justified 32fs h/l 1 0 1 20bit, msb justified 20bit, lsb justified 40fs h/l 2 1 0 20bit, msb justified 20bit, msb justified 40fs h/l default 3 1 1 iis (i 2 s) iis (i 2 s) 32fs or 40fs l/h table 3. audio data format lrck bick ( 64fs ) sdto ( o ) 0 1 2 16 1 7 1 8 20 21 31 0 1 2 31 0 1 9 1 18 0 19 1 8 19 sdti ( i ) 1 1 4 0 1 5 12 11 1 0 lch dat a rch data don?t care don?t care 4 3 2 1 13 16 1 7 18 14 1 5 1 13 20 21 12 11 4 3 2 0 bick ( 32fs ) sdti ( i ) 0 1 2 8 9 10 15 0 1 2 0 1 5 1 14 7 8 12 11 14 6 5 4 13 3 2 1 0 8 9 10 15 7 8 12 11 14 6 5 4 13 3 2 1 0 1 5 14 1 5 sdto ( o ) 1 9 18 11 12 10 9 8 7 6 5 4 1 9 19 18 11 12 10 9 8 7 6 5 4 1 9 19 figure 10. mode 0 timing lrck bick ( 64fs ) sdto ( o ) 0 1 2 12 13 14 20 21 31 0 1 2 12 13 14 20 21 31 0 1 9 1 18 0 19 1 8 8 7 6 0 19 sdti ( i ) 1 1 8 0 19 12 11 1 18 0 19 12 11 lch data rch data don?t care don?t care 8 7 6 figure 11. mode 1 timing
asahi kasei [AK4569] ms0292-e-01 2005/07 - 16 - lrck bick(64fs) sdto(o) 0 1 2 15 16 17 18 31 0 1 2 0 19 1 18 3 19 18 19 sdti(i) 14 15 14 15 lch data rch data don?t care 4 0 20 19 30 15 2 31 30 16bit 1 0 15 16 3 don?t care 0 10 sdti(i) 16 17 0 16 17 don?t care 2 1 17 18bit 0 don?t care 21 sdti(i) 18 19 2 18 19 don?t care 4 3 19 20bit 1 0 don?t care 3 10 17 18 4 20 19 2 2 4 figure 12. mode 2 timing lrck bick(64fs) sdto(o) 0 1 2 3 16 17 18 31 0 1 2 0 19 1 18 3 19 18 sdti(i) 14 15 14 15 lch data rch data don?t care 4 0 20 19 30 2 31 30 16bit 10 31617 3 don?t care 0 1 sdti(i) 16 17 0 16 17 don?t care 2 1 18bit 0 don?t care 21 sdti(i) 18 19 2 18 19 don?t care 4 3 20bit 10 don?t care 3 1 21 18 4 20 19 20 2 40 21 bick(32fs) sdti(i) 0 1 2 3 8 9 10 15 0 1 2 0 15 1 14 7 8 12 11 14 6 54 3 13 3 2 10 8910 15 7 8 12 11 14 65 4 13 3 2 10 15 14 sdto(o) 19 18 11 12 10 98 7 6 54 4 19 18 11 12 10 9 8 7 6 5 0 4 figure 13. mode 3 timing ? digital high pass filter the AK4569 has a digital high pass filter (hpf) to cancel dc-offsets in the adc and ipga. the cut-off frequency of the hpf is 3.4hz at fs=44.1khz. this filter scales with the sampling frequency (fs).
asahi kasei [AK4569] ms0292-e-01 2005/07 - 17 - ? alc operation [1] alc limiter operation during the alc limiter operation, when either lch or rch exceeds alc limiter detection level (lmth), ipga value is attenuated by alc limiter att step (lmat1-0) automatically. the ipga is then set to the same value for both channels. when zelmn = ?1?, the timeout period is set by ltm1-0 bits. the attenuation ope ration is done continuously until the input signal level becomes lmth or less. after finishing the attenuation operation, if alc bit does not change to ?0?, the operation repeats when the input signal level exceeds lmth. when zelmn = ?0?, the alc limiter operation is attenuated by the ztm1-0 bits setting. the ipga value is automatically attenuated using zero crossing detection. the alc operation of the AK4569 corresponds to the impulse noise. if the impulse noise is supplied at zelmn = ?0?, the alc limiter operation becomes faster period than a set of ztm1-0 bits. in case of zelmn = ?1?, it becomes the same period as ltm1-0 bits. [2] alc recovery operation the alc recovery operation waits for the wtm1-0 bits to be set after completing the alc limiter. if the input signal does not exceed ?alc recovery waiting counter reset level (lmth)?, the alc recovery operation is done. the ipga value is automatically incremented by this operation up to the set reference level (ref6-0) with zero crossing detection which timeout period is set by ztm1-0 bits. then the ipga value is set for both lch and rch. the alc recovery operation is done at a period set by wtm1-0 bits. when zero cross is detected at the ipga output during the wait period set by wtm1-0 bits, the alc recovery operation waits until wtm1-0 period and the next recovery operation is done. during the alc recovery operation or the recovery waiting, when either input signal level of lch or rch in ipga exceeds the alc limiter detection level (lmth), the alc recovery operation changes into the alc limiter operation immediately. when (alc recovery waiting counter reset level: lmth) (ipga output level) < (alc limiter detection level: lmth) during the alc recovery operation, the alc recovery operation wait timer is reset. therefore, when (alc recovery waiting counter reset level: lmth) > (ipga output level), the alc recovery operation wait timer starts. the alc operation of the AK4569 corresponds to the impulse noise. if the impulse noise is supplied, the alc recovery operation becomes faster period than a set of ztm1-0 or wtm1-0 bits. others: when either channel enters the limiter operation while waiting time for a zero crossing, the present alc recovery operation stops, according as the small value of ipga (a channel waiting zero crossing), the alc limiter operation is done. when both channels are waiting for the next alc recovery operation, the alc limiter operation is done from the ipga value of a point in time. ztm1-0 bits set zero crossing timeout and wtm1-0 bits set the alc recovery operation period. when the alc recovery waiting time (wtm1-0 bits) is shorter than zero crossing ti meout period (ztm1-0 bits), the alc recovery is operated by the zero crossing timeout period. therefore, in this ca se, the alc recovery operation period is not constant.
asahi kasei [AK4569] ms0292-e-01 2005/07 - 18 - [3] alc operation example the following registers should not be changed during the alc operation: ltm1-0, lmth, lmat1-0, wtm1-0, ztm1-0, ratt, ref6-0, zelmn. manual mode wr (power management control & signal select) wr ( lmat1-0, ratt, lmth ) wr ( ref6-0 ) wr ( alc= ?1?,zelmn ) wr ( ipga6-0 ) wr ( ztm1-0, w tm1-0, ltm1-0 ) wr ( alc=?0? ) ye s no * the value of ipga should be the same or smaller than ref?s. finish alc mode? alc o p eration finish alc mode and return to manual mode figure 14. registers set-up sequence at alc operation (wr=write)
asahi kasei [AK4569] ms0292-e-01 2005/07 - 19 - ? ipga operation [write operation at alc enabled] the values of ipga6-0 bits are ignored during alc operation. [write operation at alc disabled] channel independent zero crossing detection is used. if ther e are no zero crossings, then the level will change after a timeout. the ztm1-0 bits set the zero crossing timeout. when a p writes to the ipga6-0 bits, the zero crossing counter is reset and starts. when the ipga output signal detects zero crossing or a zero crossing timeout, the written value from the p becomes valid. when writing to the ipga6-0 bits continually, the control register s hould be written by an interval more than zero crossing timeout. if not, there is a possibility that each ipga of l/r channels has a different gain. [ipga gain after completing alc operation] the ipga6-0 bits are not updated by the actual gain of ipga changed during alc operation. in order to set the actual gain of ipga with the ipga6-0 bits, the ipga6-0 bits sh ould be written after zero crossing timeout period when completing alc operation (alc bit= ?1? ? ?0?).
asahi kasei [AK4569] ms0292-e-01 2005/07 - 20 - ? digital attenuator the AK4569 has a channel-independent digital attenuator (256 levels, 0.5db step). this digital attenuator is placed before the d/a converter. attl/r7-0 bits set the attenuation level (0db to ? 127db or mute) for each channel (table 19). at dattc= ?1?, attl7-0 bits control both lch and rch attenua tion levels. at dattc= ?0?, attl7-0 bits control the lch level and attr7-0 bits control the rch level. the ats bit sets the transition time between set values of att7-0 bits as either 1061/fs or 7424/fs (table 15). when ats= ?0?, a soft transition between the set values occurs (1062 levels). it takes 1061/fs (24ms@fs=44.1khz) from ffh(0db) to 00h(mute). the atts are 00h when the pmdac bi t is ?0?. when the pmdac returns to ?1?, the atts fade to their current value. digital attenuator is independent of the soft mute function. ? soft mute soft mute operation is performed in the digital domain. when smute bit goes to ?1?, the output signal is attenuated by ? (?0?) via the cycle set by tm1-0 bit (table 18). when smute bit returns to ?0?, the mute is cancelled and the output attenuation gradually changes to 0db via the cycle set by tm1-0 bits. if the soft mute is cancelled within the cycle set by tm1-0 bits after starting the operation, the attenuation is discontinued and returned to 0db. the soft mute is effective for changing the signal source without stopping the signal transmission. smute bit a ttenuation tm1-0 bit 0db - a nalog output gd gd (1) (2) (3) tm1-0 bit figure 15. soft mute function note: (1) the output signal is attenuated until ? (?0?) by the cycle set by tm1-0 bits. (2) analog output corresponding to digital input has the group delay (gd). (3) if the soft mute is cancelled within the cycle set by tm1-0 bits, the attenuation is discontinued and returned to 0db(the setting value).
asahi kasei [AK4569] ms0292-e-01 2005/07 - 21 - ? de-emphasis filter the AK4569 includes a digital de-emphasis filter (tc = 50/15 s) by iir filter corresponding to three sampling frequencies (32khz, 44.1khz and 48khz). the de-emphasis filter is enabled by setting dem1-0 bits (table 16). ? bass boost function by controlling bst1-0 bits, the low frequency boost signal can be output from dac. the setting value is common in lch and rch (table 17). the cut-off frequency (fc) of hpf depends on the external resi stor and capacitor values. table 4 shows the relationship of external resistor, capacitor, fc and output power, where load resistance of headphone is 16 ? . output level of headphone amp is 1.5vpp (typ). AK4569 hp-amp 16 ? headphone r c figure 16. external circuit example of headphone r [ ? ] c [ f] fc [hz] boost=off fc [hz] boost=mid output power [mw] 47 148.6 65 6.8 100 69.8 27 8.7 47 105.8 43 16 100 49.7 20 4.4 table 4. relationship of external circuit, output power and frequency response note: cut-off frequency (fc) at boost=mid is approximate value. ? system reset the AK4569 should be reset once by bringing pdn ?l? upon power-up. after exiting reset, vcom, ipga, adc, dac, hpl, hpr and mout switch to the power-down state. the contents of the control register are maintained until the reset is done. adc exits reset and power down state by mclk after pmadc bit is changed to ?1?, and then adc is powered up and the internal timing starts clocking by lrck ? ?. adc is in the power-down mode until mclk and lrck are input. dac also exits reset and power down state when mclk and lrck are input after pmdac= ?1?.
asahi kasei [AK4569] ms0292-e-01 2005/07 - 22 - ? power-up/down sequence 1) adc power supply pdn pin pmvcm bit clock input pmadc bit a dc internal state a in pin pd(power-down) init cycle normal operation (6) 2081/fs sdto pin (7) gd (5) (4) pd normal operation init cycle (7) gd (6) 2081/fs (7) gd (hi-z) (hi-z) don?t care don?t care hplmt, hprmt bit (1) >150ns (2) >0 (3) >0 figure 17. power-up/down sequence of adc (1) pdn pin should be set to ?h? at least 150ns after the power is supplied. (2) hplmt, hprmt and pmvcm bits should be changed to ?1? after pdn pin goes to ?h?. (3) pmadc bit should be changed to ?1? after hplmt, hprmt and pmvcm bits are changed to ?1?. (4) external clocks (mclk, bick, lrck) are needed to operate adc. (5) when pmadc bit is changed to ?1?, each ain pin is biased to vcom voltage. rising time constant is determined by input capacitor for ac coupling and input resistance. in case of ainl2/ainr2 and 1f input capacitor, time constant is = 1f x 12.5k ? = 12.5ms (typ) (6) the analog part of adc is initialized during 2081/fs (=47ms@fs=44.1khz) after exiting the power-down state. sdto is ?l? at that time. (7) digital output corresponding to analog input has the group delay (gd) of 17.0/fs(=385s@fs=44.1khz).
asahi kasei [AK4569] ms0292-e-01 2005/07 - 23 - 2) dac hp-amp power supply voltage for headphone amp is supplied from hvdd pin and centered on vcom. load resistance of headphone output is min.20 ? . when pmhpl and pmhpr bit are ?0?, headphone amplifiers are powered-down perfectly. then hpl and hpr pins are fixed to ?l? (hvss) and a capacitor of mutet pin works to avoid pop noise. power supply pdn pin pmvcm bit clock input (4) sdti pin pmdac bit dac internal state pd normal operation hpl/r pin pmhpl/r bit (5) a ttl/r7-0 bit 00h(mute) ffh(0db) (7) gd (8) 1061/fs pd normal operation 00h(mute) ffh(0db) (7) (8) (5) (6) (7) (8) don?t care (6) (7) (8) 00h(mute) (9) don?t care hplmt, hprmt bit (1) >150ns (2) >0 pd (3) >0 figure 18. power-up/down sequence of dac and hp-amp (1) pdn pin should be set to ?h? at least 150ns after the power is supplied. (2) hplmt, hprmt and pmvcm bits should be changed to ?1? after pdn pin goes to ?h?. (3) pmdac, pmhpl, pmhpr bits should be changed to ?1? a nd hplmt, hprmt bits should be changed to ?0? after hplmt, hprmt, pmvcm bits are changed to ?1?. once pmhpl and pmhpr bits are changed to ?1?, hplmt and hprmt bits should be inverted from pmhpl and pmhpr bits respectively. (4) external clocks (mclk, bick, lrck) are needed to operate dac. when pmdac bit = ?0?, these clocks can be stopped. headphone amp can operate without these clocks. (5) rise time of headphone amp is determined by external capacitor of mutet pin. when c=1f, rise time constant of headphone amp: = 100ms (6) fall time of headphone amp is determined by output capacitor for ac coupling. when c=100f, fall time constant of headphone amp: = 200ms (7) analog output corresponding to digital input has th e group delay (gd) of 16.8/fs(=381s@fs=44.1khz). (8) ats bit sets transition time of digital attenuator. default value is 1061/fs(=24ms@fs=44.1khz). (9) power supply should be switched off after headphone amp is powered down (hpl/r pins become ?l?).
asahi kasei [AK4569] ms0292-e-01 2005/07 - 24 - 3) dac mout power supply pdn pin pmvcm bit clock input (4) sdti pin pmdac bit dac internal state pd(power-down) normal operation pmmo bit a ttl/r7-0 bit 00h(mute) ffh(0db) mout pin (5) mmute, a ttm3-0 bit 10h(mute) 0fh(0db) (6) g d (7) 1061/fs (hi-z) pd normal operation 00h(mute) ffh(0db) (hi-z) (6) (7) (5) (5) (6) (7) don?t care hplmt, hprmt bit don?t care (1) >150ns (2) >0 (3) >0 figure 19. power-up/down sequence of dac and mout (1) pdn pin should be set to ?h? at least 150ns after the power is supplied. (2) hplmt, hprmt and pmvcm bits should be changed to ?1? after pdn pin goes to ?h?. (3) pmdac and pmmo bits should be changed to ?1? after hplmt, hprmt and pmvcm bits are changed to ?1?. (4) external clocks (mclk, bick, lrck) are needed to operate dac. when pmdac= ?0?, these clocks can be stopped. mout buffer can operate without these clocks. (5) when pmmo bit is changed to ?1?, pop noise is output from mout pin. (6) analog output corresponding to digital input has th e group delay (gd) of 16.8/fs(=381s@fs=44.1khz). (7) ats bit sets transition time of digital atte nuator. default value is 1061/fs(=24ms@fs=44.1khz).
asahi kasei [AK4569] ms0292-e-01 2005/07 - 25 - 4) lin/rin/min hp-amp, mout power supply pdn pin pmvcm bit hpl/r pin (5) mout pin (7) mmute, a ttm3-0 bit 10h(mute) 0fh(0db) (hi-z) (hi-z) (7) (7) (5 ) (6) lin/rin/min pin (4) (hi-z) (hi-z) pmhpl/r bit, pmmo bit don?t care hplmt, hprmt bit (1) >150ns (2) >0 (3) >0 figure 20. power-up/down sequence of lin/rin/min, hp-amp and mout (1) pdn pin should be set to ?h? at least 150ns after the power is supplied. (2) hplmt, hprmt and pmvcm bits should be changed to ?1? after pdn pin goes to ?h?. (3) pmhpl, pmhpr, pmmo bits should be changed to ?1? and hplmt, hprmt bits should be changed to ?0? after hplmt, hprmt, pmvcm bits are changed to ?1?. once pmhpl and pmhpr bits are changed to ?1?, hplmt and hprmt bits should be inverted from pmhpl and pmhpr bits respectively. (4) when pmhpl, pmhpr or pmmo bit is changed to ?1?, lin, rin and min are biased to vcom voltage. rising time constant is determined by input capacitor for ac coupling and input resistance 50k ? (typ). in case of 0.1f input capacitor, time constant is = 0.1f x 50k ? = 5ms (typ) (5) rise time of headphone amp is determined by external capacitor of mutet pin. when c=1f, rise time constant of headphone amp: = 100ms (6) fall time of headphone amp is determined by output capacitor for ac coupling. when c=100f, fall time constant of headphone amp: = 200ms (7) when pmmo bit is changed to ?1?, pop noise is output from mout pin.
asahi kasei [AK4569] ms0292-e-01 2005/07 - 26 - ? serial control interface internal registers may be written via to the 3 wire p interface pins (csn, cclk and cdti). the data on this interface consists of chip address (2bits, fixed to ?10?), read/write ( 1bit, fixed to ?1?, write only), register address (msb first, 5bits) and control data (msb first, 8bits). address and da ta is clocked in on the rising edge of cclk. for write operations, data is latched after a low-to-high transition of csn. the clock speed of cclk is 5mhz(max). the value of internal registers is initialized at pdn= ?l?. cdti cclk csn c1 0 1234567 8 9 10 11 12 13 14 15 d4 d5 d6 d7 a1 a2 a3 a4 r/w c0 a0 d0 d1 d2 d3 c1-c0: chip address (fixed to ?10?) r/w: read/write (fixed to ?1? : write only) a4-a0: register address d7-d0: control data figure 21. control interface
asahi kasei [AK4569] ms0292-e-01 2005/07 - 27 - ? register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management hprmt hplmt pmmo pmhpr pmhpl pmdac pmadc pmvcm 01h input select 0 0 0 adm inr2 inr1 inl2 inl1 02h timer select 0 0 ztm 1 ztm0 wtm1 wtm0 ltm1 ltm0 03h alc mode control 1 0 0 alc zelmn lmat1 lmat0 ratt lmth 04h alc mode control 2 0 ref6 ref5 ref4 ref3 ref2 ref1 ref0 05h ipga control 0 ipga6 ipga5 ipga4 ipga3 ipga2 ipga1 ipga0 06h mode control mckac mckpd 0 ats hpm dif1 dif0 dfs 07h dac control tm1 tm0 smute dattc bst1 bst0 dem1 dem0 08h output select 0 0 0 minr rinr dacr minl linl dacl 09h output select 1 0 0 0 0 minm rinm linm dacm 0ah dac lch att attl7 attl6 a ttl5 attl4 attl3 attl2 attl1 attl0 0bh dac rch att attr7 attr6 attr5 attr4 attr3 attr2 attr1 attr0 0ch mout att 0 0 0 mmute attm3 attm2 attm1 attm0 all registers inhibit writ ing at pdn pin = ?l?. note: unused bits must contain a ?0? value. note: for addresses from 0dh to 1fh, data must not be written.
asahi kasei [AK4569] ms0292-e-01 2005/07 - 28 - ? register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management hprmt hplmt pmmo pmhpr pmhpl pmdac pmadc pmvcm default 0 0 0 0 0 0 0 0 pmvcm: power management for vcom block 0: power off (default) 1: power on pmadc: power management for ipga and adc blocks 0: power off (default) 1: power on mclk should be present when pmadc bit= ?1?. pmdac: power management for dac blocks 0: power off (default) 1: power on when pmdac bit is changed from ?0? to ?1?, dac is powered-up to the current register values (att value, sampling rate, etc). pmhpl: power management for lch of headphone amp 0: power off (default). hpl pin becomes hvss(0v). 1: power on pmhpr: power management for rch of headphone amp 0: power off (default). hpr pin becomes hvss(0v). 1: power on pmmo: power management for mono output 0: power off (default) mout pin becomes hi-z. 1: power on hplmt: mute for lch of headphone amp 0: normal operation (default). mutet pin is connected to vcom pin internally. 1: mute. mutet pin is connected to hpl pin internally. hplmt: mute for rch of headphone amp 0: normal operation (default). mutet pin is connected to vcom pin internally. 1: mute. mutet pin is connected to hpr pin internally. hplmt hprmt mutet 0 0 connected to vcom 0 1 connected to hpr 1 0 connected to hpl 1 1 connected to hpl,hpr table 5. mutet internal connection all blocks can be powered-down by setting the pdn pin to ?l? regardless of register values setup. in this case, all control register values are initialized.
asahi kasei [AK4569] ms0292-e-01 2005/07 - 29 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h input select 0 0 0 adm inr2 inr1 inl2 inl1 default 0 0 0 0 0 1 0 1 inl2-1: select on/off of ipga lch input. 0: off 1: on default: inl2=0, inl1=1 inr2-1: select on/off of ipga rch input. 0: off 1: on default: inr2=0, inr1=1 adm: mono recording mode 0: stereo (default) 1: mono when adm= ?1?, input signal to ainl1 or ainl2 pin is input to both lch and rch of adc.
asahi kasei [AK4569] ms0292-e-01 2005/07 - 30 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h timer select 0 0 ztm 1 ztm0 wtm1 wtm0 ltm1 ltm0 default 0 0 0 0 0 0 0 0 ltm1-0: alc limiter operation period (table 6) when zero crossing is disabled ( zelmn = ?1?), the ipga value is ch anged immediately by alc limiter operation. when the ipga value is changed continuously, the change is done by the period specified by ltm1-0 bits. default: ?00?. alc limiter operation period ltm1 ltm0 8khz 16khz 44.1khz 0 0 0.5/fs 63 s 31 s 11 s default 0 1 1/fs 125 s 63 s 23 s 1 0 2/fs 250 s 125 s 45 s 1 1 4/fs 500 s 250 s 91 s table 6. alc limiter operation period at zero crossing disable (zelmn bit= ?1?) wtm1-0: alc recovery waiting period (table 7) wtm1-0 bits set the recovery operation period when any limiter operation does not occur during an alc operation. default: ?00?. alc recovery operation waiting period wtm1 wtm0 8khz 16khz 44.1khz 0 0 128/fs 16ms 8ms 2.9ms default 0 1 256/fs 32ms 16ms 5.8ms 1 0 512/fs 64ms 32ms 11.6ms 1 1 1024/fs 128ms 64ms 23.2ms table 7. alc recovery operation waiting period ztm1-0: alc zero crossing timeout period (table 8) when ipga output detects zero crossing or timeout, the ipga value is changed by a p write operation, alc recovery operation, or alc limiter operation. default: ?00?. zero crossing timeout period ztm1 ztm0 8khz 16khz 44.1khz 0 0 128/fs 16ms 8ms 2.9ms default 0 1 256/fs 32ms 16ms 5.8ms 1 0 512/fs 64ms 32ms 11.6ms 1 1 1024/fs 128ms 64ms 23.2ms table 8. zero crossing timeout period
asahi kasei [AK4569] ms0292-e-01 2005/07 - 31 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h alc mode control 1 0 0 alc zelmn lmat1 lmat0 ratt lmth default 0 0 0 0 0 0 0 0 lmth: alc limiter detection level / recovery waiting counter reset level (table 9) lmth alc limiter detection level alc recovery waiting counter reset level 0 adc input ? 6.0dbfs ? 6.0dbfs > adc input ? 8.0dbfs default 1 adc input ? 4.0dbfs ? 4.0dbfs > adc input ? 6.0dbfs table 9. alc1 limiter detection level / recovery waiting counter reset level ratt: alc recovery gain step (table 10) during the alc recovery operation, the number of steps changed from the current ipga value is set. for example, when the current ipga value is 3fh, ratt = ?1? is set, the ipga changes to 41h due to the alc recovery operation, the output signal level is gained by 1db (=0.5db x 2). when the ipga value exceeds the reference level (ref6-0 bits), the ipga value does not increase. ratt gain step 0 1 default 1 2 table 10. alc recovery gain step setting lmat1-0: alc limiter att step (table 11) during the alc limiter operation, when either lch or rch exceeds the alc limiter detection level set by lmth bit, lmat1-0 bits set the number of steps attenuated from the current ipga value. for example, when the current ipga value is 3fh when lmat1-0 bit = ?11?, the ipga value changes to 3bh by the alc limiter operation, the input signal level is attenuated by 2db (=0.5db x 4). when the attenuation value exceeds ipga = ?00h? (mute), it clips to ?00h?. lmat1 lmat0 att step 0 0 1 default 0 1 2 1 0 3 1 1 4 table 11. alc limiter att step setting zelmn: zero crossing de tection enable at al c limiter operation 0: enable (default) 1: disable in case of zelmn = ?0?, when ipga output detects zero crossing or ti meout, the ipga value is changed by the alc operation. zero crossing timeout is the same as alc re covery operation. in case of zelmn = ?1?, the ipga value is changed immediately. alc: alc enable flag 0: alc disable (default) 1: alc enable alc is enabled at alc bit is ?1?. default: ?0? (disable).
asahi kasei [AK4569] ms0292-e-01 2005/07 - 32 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h alc mode control 2 0 ref6 ref5 ref4 ref3 ref2 ref1 ref0 default 0 0 1 1 1 1 1 1 ref6-0: reference value at alc recovery operation, 0.5db step, 103 levels, default: ?3fh? (table 12) during the alc recovery operation, if the ipga value exceeds the set reference value by gain operation, ipga does not become larger than the reference value. for example, when ref= ?40h?, ratt= ?1? (2 step) and ipga= ?3fh?, then ipga is going to become 3fh + 2step = 41h, but ipga becomes 40h in fact, since ref=40h. gain data ainl1, ainr1 (line in) ainl2, ainr2 (mic in) 67h +20.0db +32.0db 66h +19.5db +31.5db 65h +19.0db +31.0db : : : 3fh 0db +12.0db default : : : 27h ? 12.0db 0db : : : 02h ? 30.5db ? 18.5db 01h ? 31.0db ? 19.0db 00h mute ( ? ) mute ( ? ) table 12. reference value setting at alc recovery operation addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h ipga control 0 ipga6 ipga5 ipga4 ipga3 ipga2 ipga1 ipga0 default 0 0 1 1 1 1 1 1 ipga6-0: input analog pga, 0.5db step, 103 levels, default: ?3fh? (table 13) when ipga gain is changed, ipga6-0 bits should be written while pmadc bit is ?1? and alc bit is ?0?. ipga gain is reset when pmadc bit is ?0?, and then ipga operation starts from the default value when pmadc is changed to ?1?. when alc bit is changed from ?1? to ?0?, ipga holds the last gain value set by alc operation. gain data ainl1, ainr1 (line in) ainl2, ainr2 (mic in) 67h +20.0db +32.0db 66h +19.5db +31.5db 65h +19.0db +31.0db : : : 3fh 0db +12.0db default : : : 27h ? 12.0db 0db : : : 02h ? 30.5db ? 18.5db 01h ? 31.0db ? 19.0db 00h mute ( ? ) mute ( ? ) table 13. input gain setting
asahi kasei [AK4569] ms0292-e-01 2005/07 - 33 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h mode control mckac mckpd 0 ats hpm dif1 dif0 dfs default 0 0 0 0 0 1 0 0 dfs: sampling speed mode select (table 2) dif1-0: audio data interface format default: ?10? (mode 2) hpm: mono output select of headphone 0: normal operation (default) 1: mono. (l+r)/2 signals from the dac are output to both lch and rch of headphone. setting of hpm bit is enabled only at dacl=dacr= ?1?. dacl hpm hpl pin output 0 x no output from dac default 0 output from lch of dac 1 1 output (l+r)/2 from dac table 14. mono output select of headphone (note. rch is same.) ats: digital attenuator transition time setting (table 15) att speed ats 0db to mute 1 step 0 1061/fs 4/fs default 1 7424/fs 29/fs table 15. transition time between set values of att7-0 bits mckpd: mclk input buffer control 0: enable (default) 1: disable when mclk input with ac coupling is stopped, mckpd bit should be set to ?1?. mckac: mclk input mode select 0: cmos input (default) 1: ac coupling input
asahi kasei [AK4569] ms0292-e-01 2005/07 - 34 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h dac control tm1 tm0 smute dattc bst1 bst0 dem1 dem0 default 0 0 0 0 0 0 0 1 dem1-0: de-emphasis filter frequency select dem1 dem0 de-emphasis 0 0 44.1khz 0 1 off default 1 0 48khz 1 1 32khz table 16. de-emphasis filter frequency select bst1-0: low frequency boost function select bst1 bst0 boost 0 0 off default 0 1 min 1 0 mid 1 1 max table 17. low frequency boost select dattc: dac digital attenuator control mode select 0: independent (default) 1: dependent at dattc= ?1?, attl7-0 bits cont rol both lch and rc h attenuation level, while register values of attl7-0 bits are not written to attr7-0 bits. at dattc= ?0?, attl7-0 bits control lch level and attr7-0 bits control rch level. smute: soft mute control 0: normal operation (default) 1: dac outputs soft-muted tm1-0: soft mute time select tm1 tm0 cycle 0 0 1024/fs default 0 1 512/fs 1 0 256/fs 1 1 128/fs table 18. soft mute time setting
asahi kasei [AK4569] ms0292-e-01 2005/07 - 35 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h output select 0 0 0 minr rinr dacr minl linl dacl default 0 0 0 0 0 0 0 0 dacl: dac lch output signal is added to lch of headphone amp. 0: off (default) 1: on linl: input signal to lin pin is added to lch of headphone amp. 0: off (default) 1: on minl: input signal to min pin is added to lch of headphone amp. 0: off (default) 1: on dacr: dac rch output signal is added to rch of headphone amp. 0: off (default) 1: on rinr: input signal to rin pin is added to rch of headphone amp. 0: off (default) 1: on minr: input signal to min pin is added to rch of headphone amp. 0: off (default) 1: on dacl/dacr - + hpl/hpr pin lin/rin pin min pin hp-amp r r r r linl/rinr bit minl/minr bi t dacl/dacr bit figure 22. summation circuit for headphone amp output at hpm=0, gain of summation is 0db for all input path.
asahi kasei [AK4569] ms0292-e-01 2005/07 - 36 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 09h output select 1 0 0 0 0 minm rinm linm dacm default 0 0 0 0 0 0 0 0 dacm: dac lch and rch outputs are added to mout buffer amp. summation gain is ? 6db for each channel. 0: off (default) 1: on linm: input signal to lin pin is added to mout buffer amp. 0: off (default) 1: on rinm: input signal to rin pin is added to mout buffer amp. 0: off (default) 1: on minm: input signal to min pin is added to mout buffer amp. 0: off (default) 1: on dacr - + mout pin lin pin rin pin 2r r 2r 2r min pin r dacl 2r linm bit rinm bit minm bit dacm bit figure 23. summation circuit for mout gain of summation is 0db for min and ? 6db for lin, rin, dacl and dacr.
asahi kasei [AK4569] ms0292-e-01 2005/07 - 37 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah dac lch att attl7 attl6 a ttl5 attl4 attl3 attl2 attl1 attl0 0bh dac rch att attr7 attr6 attr5 attr4 attr3 attr2 attr1 attr0 default 0 0 0 0 0 0 0 0 attl7-0: setting of th e attenuation value of output signal from dacl attr7-0: setting of the attenuation value of output signal from dacr the AK4569 has channel-independent digital attenuator (256 levels, 0.5db step). this digital attenuator is placed before d/a converter. attl/r7-0 bits set the attenuation level (0db to ? 127db or mute) of each channel. digital attenuator is independent of soft mute function. attl/r7-0 attenuation ffh 0db feh ? 0.5db fdh ? 1.0db fch ? 1.5db : : : : 02h ? 126.5db 01h ? 127.0db 00h mute ( ? ) default table 19. digital volume att values addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ch mout att 0 0 0 mmute attm3 attm2 attm1 attm0 default 0 0 0 1 0 0 0 0 attm3-0: analog volume control for mout mmute: mute control for mout 0: normal operation. attm3-0 bits control attenuation value. 1: mute. attm3-0 bits are ignored. (default) mmute attm3-0 attenuation 0fh 0db 0eh ? 2db 0dh ? 4db 0ch ? 6db : : : : 01h ? 28db 0 00h ? 30db 1 x mute default table 20. mout volume att values
asahi kasei [AK4569] ms0292-e-01 2005/07 - 38 - system design figure 24 shows the system connection diagram. an evaluation board [akd4569] is available which demonstrates the optimum layout, power supply arrangements and measurement results. ainl1 28 27 26 25 24 23 22 pdn 1 2 3 4 5 6 7 csn cdti lrck mclk bick ainr1 ainl2 avss vcom sdti 21 20 19 18 17 16 15 8 9 10 11 12 13 14 dvss sdto dvdd hvss hpr mutet hpl to p vi e w hvdd ainr2 avdd cclk mout min rin lin vref 0.1 + 0.1 2.2 + 4.7 0.1 1 6.8 100 + 16 6.8 100 + 16 headphone 0.1 0.1 10 + 10 analog supply: 2.5 3.6v AK4569 p dsp dir a nalog ground digital ground figure 24. typical connection diagram
asahi kasei [AK4569] ms0292-e-01 2005/07 - 39 - 1. grounding and power supply decoupling the AK4569 requires careful attention to power supply and grounding arrangements. avdd is usually supplied from the analog power supply in the system and dvdd is supplied from avdd via a 10 ? resistor. alternatively if avdd, dvdd and hvdd are supplied separately, the power up sequence is not critical. avss, dvss and hvss must be connected to the analog ground plane. system analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as close to the AK4569 as possible, with the small value ceramic capacitors being the nearest. 2. internal voltage reference internal voltage reference is output on the vref pin (typ. 2.1v). an electrolytic capacitor 4.7 f in parallel with a 0.1 f ceramic capacitor is attached between vref and avss to eliminate the effects of high frequency noise. vcom is 1.25v(typ) and is a signal ground of this chip. a 2.2 f electrolytic capacitor in parallel with a 0.1 f ceramic capacitor should be connected between vcom and avss to eliminate the effects of high frequency noise. a ceramic capacitor should be connected to vcom pin and located as close as possible to the AK4569. no load current may be drawn from vref and vcom pins. all signals, especially clocks, should be kept away from the vcom and vref pins in order to avoid unwanted coupling into the AK4569. 3. analog inputs the analog inputs are single-ended and the input resistance 50k ? (typ) for ainl1/ainr1 pins and 12.5k ? (typ) for ainl2/ainr2 pins. the input signal range is 1.5vpp centered on vcom voltage. usually, the input signal cuts dc with a capacitor. the cut-off frequency is fc=(1/2 rc). the AK4569 can accept input voltages from avss to avdd. the adc output data format is 2?s complement. the adc?s dc offset is removed by the internal hpf (fc=3.4hz@fs=44.1khz). 4. analog outputs the analog outputs are single-ended outputs and 1.5vpp(typ) centered on the vcom voltage. the input data format is 2?s compliment. the output voltage is a positive full scale for 7ffffh(@20bit) and negative full scale for 80000h(@20bit). the ideal output is vcom voltage for 00000h(@20bit). if the noise generated by the delta-sigma modulator beyond the audio band causes problems, attenuation by an external filter is required. dc offsets on the analog outputs is eliminated by ac coupling since the analog outputs have a dc offset equal to vcom plus a few mv.
asahi kasei [AK4569] ms0292-e-01 2005/07 - 40 - ? application circuit example sdto lrck bick adc hpf audio i/f controller ipga a inl1 a inl2 a inr1 a inr2 hp-amp hpl dac hpr mout lin rin min hvdd hvss mutet avdd avss boost datt sdti control mclk csn cclk cdti register pdn dvdd dvss ak4116 AK4569 rx mcko bick lrck daux sdto s/pdif xti dsp clkout bick lrck sdti sdto csn cclk cdti up cdto hp-amp ipga & adc mout dac vcom vcom vref vref figure 25. application circuit example
asahi kasei [AK4569] ms0292-e-01 2005/07 - 41 - 1) analog recording sdto lrck bick adc hpf audio i/f controller ipga a inl1 a inl2 a inr1 a inr2 hp-amp hpl dac hpr mout lin rin min hvdd hvss mutet avdd avss boost datt sdti control mclk csn cclk cdti register pdn dvdd dvss ak4116 AK4569 rx mcko bick lrck daux sdto xti dsp clkout bick lrck sdti sdto csn cclk cdti up cdto hp-amp ipga & adc mout dac vcom vcom vref vref figure 26. clock and data flow during analog recording (with dac monitor)
asahi kasei [AK4569] ms0292-e-01 2005/07 - 42 - 2) digital recording sdto lrck bick adc hpf audio i/f controller ipga a inl1 a inl2 a inr1 a inr2 hpl hpr mout lin rin min hvdd hvss mutet avdd avss sdti control mclk csn cclk cdti register pdn dvdd dvss ak4116 AK4569 rx mcko bick lrck daux sdto s/pdif xti dsp clkout bick lrck sdti sdto csn cclk cdti up cdto ipga & adc hp-amp dac boost datt hp-amp mout dac vcom vcom vref vref figure 27. clock and data flow during digital recording (with dac monitor)
asahi kasei [AK4569] ms0292-e-01 2005/07 - 43 - 3) playback sdto lrck bick adc hpf audio i/f controller ipga a inl1 a inl2 a inr1 a inr2 hp-amp hpl dac hpr mout lin rin min hvdd hvss mutet avdd avss boost datt sdti control mclk csn cclk cdti register pdn dvdd dvss ak4116 AK4569 rx mcko bick lrck daux sdto xti dsp clkout bick lrck sdti sdto csn cclk cdti up cdto hp-amp ipga & adc mout dac vcom vcom vref vref figure 28. clock and data flow during playback
asahi kasei [AK4569] ms0292-e-01 2005/07 - 44 - package 28pin qfn (unit: mm) 0 . 2 5 0 . 1 0 5.0 0.10 5.2 0.20 5.0 0.10 0.2 + 0.1 0 - 0.20 5.2 0.20 0.50 0.22 0.05 28 22 1 8 21 0.05 m 21 15 14 8 7 1 22 45 45 0.21 0.05 0.02 + 0.03 - 0.02 0.78 + 0.17 - 0.28 0.80 + 0.20 - 0.00 0.05 7 14 15 4 - c 0 . 6 0.60 0.10 28 note: the black parts of back package should be open. ? package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder (pb free) plate
asahi kasei [AK4569] ms0292-e-01 2005/07 - 45 - marking 4569 xxxx 1 xxxx : date code identifier (4 digits) revision history date (yy/mm/dd) revision reason page contents 04/02/20 00 first edition 05/07/19 01 error correct 21 bass boost function figure 16: ?ak4566? ? ?AK4569? 38-43 system design figures 24 to 28: ?ak4566? ? ?AK4569? 45 marking ?4566? ? ?4569? important notice ? these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. ? akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: a. a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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